1. Field of the Invention
The present invention relates generally to a memory device. More particularly, the invention relates to a NAND flash memory device and a method of programming the same.
A claim of priority is made to Korean Patent Application No. 2004-117618 filed Dec. 31, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A NAND flash memory device comprises a plurality of memory cells arranged in a matrix. The matrix is divided into a plurality of memory blocks and each of the plurality of memory blocks is divided into a plurality of pages. The NAND flash memory device performs erase operations a block at a time and it performs read and program operations a page at a time.
FIG. 1 is a diagram of a conventional NAND flash memory device disclosed in Korean Patent Application No. 2001-56526.
Referring to FIG. 1, a NAND flash memory device 100 comprises a memory cell array 110, a row decoder circuit 120, a switch circuit 130, a control circuit 140, a page buffer 150, and a column pass gate 160.
Memory cell array 110 comprises first strings 112e connected to a plurality of first bitlines BLe0 through BLeN and second strings 112o connected to a plurality of second bitlines BLo0 through BLoN. The first and second strings are formed in an alternating arrangement known as a shielded bitline architecture. The purpose of the shielded bitline architecture is to reduce coupling capacitance between the first and second bitlines.
Each string comprises first and second select transistors ST and GT and a plurality of cell transistors M0 through MM. First and second select transistors ST and GT and cell transistors M0 through MM are connected in series.
Gates of first and second select transistors ST and GT are respectively connected to string and ground select lines SSL and GSL. Gates of cell transistors M0 through MM are respectively connected to corresponding wordlines WL0 through WLm. Lines SSL, GSL, and WL0 through WLm are connected to row decoder circuit 120. A source of second select transistor GT is electrically connected to a common source line CSL.
Row decoder circuit 120 selects a memory block and a wordline in response to a predetermined input address and supplies a wordline voltage to the selected wordline as a program voltage. Row decoder circuit 120 selects the memory block by activating (i.e., setting to a logic level “high”) a block select line BLKWL. While block select line BLKWL is activated, the wordline voltage is applied to the selected wordline.
NAND flash memory device 100 further comprises a PMOS transistor P4 and an NMOS transistor N4. PMOS transistor P4 pre-charges a node VIRPWR to a power supply voltage Vcc in response to a control signal VIRPWRP. NMOS transistor N4 discharges node VIRPWR to ground in response to a control signal VIRPWRN.
NAND flash memory device 100 comprises third bitlines connecting nodes X1 to page buffer 150. Nodes X1 are connected pairs of first and second bitlines as illustrated in FIG. 1. First NMOS transistors Ne1 selectively connect first bitlines BLe0 to BLeN to corresponding nodes X1 in response to a control signal BLSHFe.
Second NMOS transistors No1 selectively connect second bitlines BLo0 through BLoN to corresponding nodes X1 in response to a control signal BLSHFo. Third NMOS transistors N2 selectively connect the third bitlines to page buffer 150 in response to a control signal BLSLT. Control circuit 140 generates control signals BLSHFe, BLSHFo, and BLSLT using a timing scheme illustrated in FIG. 2.
Page buffer 150 comprises latches 151 storing data to be programmed in memory cell array 110. Latches 151 are connected to the third bitlines. Column pass gate 160 provides predetermined input data to page buffer 150.
FIG. 2 is a waveform timing diagram illustrating a program operation of the NAND flash memory device in FIG. 1. The program operation of FIG. 2 is performed using a two-stage bitline setup technique described below. In the two-stage bitline setup technique, bitline voltages are established, or “set up” by first precharging the bitlines to a power source voltage Vcc and then selectively discharging some of the bitlines according to the input data stored in page buffer 150. In other words, the term “bitline setup” is used to denote a process of establishing bitline voltages used in a program operation of the semiconductor device. Once the bitline voltages are “set up”, a wordline voltage is applied to the wordline to program the NAND flash memory device.
Referring to FIG. 2, first and second bitlines BLe0 through BLeN and BLo0 through BLoN are pre-charged during a first bitline setup interval SETUP1. In interval SETUP1, control signals VBLe and VBLo are set to power supply voltage Vcc. As a result, first and second bitlines BLe0 through BLeN and BLo0 through BLoN are driven to power supply voltage Vcc. Control signal BLSLT is maintained at a logic level “low” during interval SETUP1. NMOS transistors N2 are turned off by the control signal BLSLT, so that the third bitlines are disconnected from page buffer 150.
In a second bitline setup interval SETUP2, third control signal BLSLT has a reference voltage VREF lower than power supply voltage Vcc, and control signal BLSHFe is at logic level “high”. NMOS transistors Ne1 are all turned on by control signal BLSHFe to connect latches 151 in page buffer 150 to respective first bitlines BLe0 through BLeN. First bitlines are selectively discharged according to data stored in latches 151. For example, where one of latches 151 stores a logical ‘0’, a corresponding one of first bitlines BLe0 through BLeN is discharged. In contrast, where one of latches 151 stores a logical ‘1’, a corresponding one of first bitlines BLe0 through BLeN is maintained at power supply voltage Vcc.
Following interval SETUP2, a program voltage is supplied to a selected wordline during a program interval. After the program interval, first and second bitlines BLe0 through BLeN and BLo0 through BLoN are all discharged.
Third NMOS transistors N2 are simultaneously turned on during bitline setup interval SETUP2 and first or second NMOS transistors Ne1 or No1 are turned on during interval SETUP1. Because third NMOS transistors N2 are turned on at the same time, bitlines corresponding to transistors N2 are simultaneously discharged according to data stored in latches 151. In other words, bitlines are simultaneously discharged by corresponding latches 151 storing data ‘0’.
Where bitlines are simultaneously discharged, a voltage at string select line SSL drops due to a coupling capacitance between the bitlines and string select line SSL. As the voltage at string select line SSL drops, a voltage at block select line BLKWL is also lowered due to a coupling capacitance between string select line SSL and block select line BLKWL. Lowering the voltage at block select line BLKWL prevents block select transistors controlled by block select line BLKWL from being turned on. Where the block select transistors controlled by block select line BLKWL are not turned on, the program voltage fails to drive the selected wordline.
The failure of the program voltage to drive the selected wordline can lead to program failures, e.g., un-programmed memory cells. In order to overcome program failures, multiple program loops are often performed on the selected memory cell using an increasing program voltage. Typically, the program voltage is increased in a stepwise fashion for each additional program loop. Unfortunately, the increase in the program voltage can cause some unexpected or undesired results. For example, where the coupling capacitance is low because only a few memory cells are discharged, some of the memory cells may be over-programmed by the increased program voltage.
In order to avoid problems caused by the coupling capacitance, a NAND flash memory device with a reduced coupling capacitance is needed.